1. Field of the Invention
The embodiments described herein relate generally to the field of automated test equipment (ATE) and, more particularly, to test equipment that performs integrated circuit (IC) scan tests.
2. Description of Related Art
In current applications for the integrated circuit (IC) industry, with the demand for higher throughput of devices, state-of-the-art automated test equipment ATE presents a resource limitation problem. Two particular resources of relevance are scan vector memory and scan channels. The insufficiency of these resources at the ATE system level is translated into a production test throughput limitation due to the inability of state-of-the-art ATEs to test multiple devices on a single device under test (DUT) board.
Traditionally in the semiconductor IC industry, to achieve scan test results that keep up with production demands, the solution is to increase ATE resources, such as acquiring more scan vector memory and adding more scan channels on the ATE, or simply to replace the existing ATE structure with one that has more resource capabilities for the implementation of the scan test. This approach unduly increases the overall cost of the test system and drives up the cost of production.
In general, scan tests performed by existing ATE systems take place at a slow speed, normally with a 10 MHz-100 MHz clock rate. The loose timing requirements imposed by these systems have an adverse effect on the overall speed of the testing protocol, and even on the accuracy of the results.
What is needed is a method and an apparatus to increase the resource capabilities of existing ATE systems, without the need to expand/upgrade ATE resources. Also, there is a need for a faster measurement protocol to be implemented externally to the ATE, with better timing control and more precise clocking mechanisms. The ultimate result will be to reduce investment costs on ATE hardware for the industry, with the consequent reduction in overall product cost.